Episode summary
What will computer chips look like in 2045?
Dwarkesh Podcast
· · 1 hr 9 min · Hosts: Dwarkesh Patel
Summary
Intel’s leadership argues that AI has created the biggest demand shock the semiconductor industry has ever seen, forcing foundries to improve both wafer output and what each chip can do. The episode centers on how Intel is trying to ramp 14A and 18A while avoiding the mistakes of 10 nanometer, where too much innovation and immature EUV adoption helped push schedules off track. The guest emphasizes that modern process development is now a disciplined sequence of maturity gates, defect analysis, and customer-by-customer tradeoffs rather than a simple march toward smaller transistors.
A major theme is that future gains will come from a mix of new transistor structures, new materials, and new packaging. The discussion covers gate-all-around, backside power, CFET, ruthenium interconnects, and hybrid bonding, with the argument that each technology only makes sense when its manufacturing and integration problems can be solved at scale. The guest also says Intel’s architectural choices differ from TSMC’s, which changes whether High-NA EUV is economical.
The episode closes on a supply-side constraint: even if AI companies are willing to pay, output is limited by equipment, supplier capacity, and the reuse rate of existing tool sets. The guest says Intel could likely double leading-edge wafer output with today’s global stock of tools, but not 10x it, and argues that scale, yield, and timing matter more than tiny performance deltas.
Key takeaways
- The guest says AI demand is 40-50% above Intel’s maximum capacity, making supply-chain bottlenecks the central constraint on chip growth.
- Intel’s 10 nanometer delay taught the company to limit how much innovation it tries to stuff into one node and to protect schedule predictability.
- The guest says 14A will use High-NA EUV and backside power in a way that makes the tool economically attractive for Intel but not necessarily for TSMC.
- Ruthenium may beat copper only at very tight pitches, showing that materials choices depend on crossover points rather than permanent winners.
- The guest says Intel could probably double leading-edge wafer output with today’s tool stock, but not 10x it, even with strong AI demand.
Notable quotes
“There’s never been as big a shock to the semiconductor industry as the current surge in demand from AI”
“we need to limit the amount of innovation we put in there to make sure that we keep it on schedule”
“you don’t want to tackle something before you have to”
“the architecture of our technology versus TSMC’s, we make different conclusions off of the same tool set”
“Not 10X, but probably 2X, yes”
How the episode opens
There’s never been as big a shock to the semiconductor industry as the current surge in demand from AI. AI is driving incredible computing demand. Easily 40-50% above our maximum capacity, which I’ve never seen before.
Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do. But the production of these chips is bottlenecked by tools that Intel buys from their suppliers.
Most famously, ASML’s EUV machines. If they don’t have the equipment, they can’t make the chips here. I spent two days touring Intel’s fabs to prepare for these interviews with its leadership.
I wanted to understand what it takes to manufacture the world’s most advanced chips and how hardware is shaping the future of AI. I’m joined by Chris Auth, who leads development of all the processes that are currently under manufacturing. The thing I want to understand in more concrete detail is how the development of a new process actually happens.
If 14A is going to come out in three years or two years from now, what is happening from now till then? I want you to walk me through as much detail as you can, everything from the level of “how is the yield improving? to what kind of telemetry you guys look at?
What kind of experiments do you guys run? I want to understand what is going to happen over the next two years as concretely as possible. 14A has been in development for about three-plus years at this stage, so quite a bit of pre-work has been done to get it to the stage that it’s at right now.
Right now, we’re getting very close to where we’re finalizing the process.
From the episode’s captions: roughly the first two minutes, lightly cleaned. Keep watching on YouTube →
Topics
- chip design
- transistor architecture
- euv lithography
- hybrid bonding
- ai semiconductor supply
Companies and tickers mentioned
- INTC
- TSM
- Intel
- TSMC
Watch the episode
Watch “What will computer chips look like in 2045?” on YouTube
Summary, takeaways and quote selection by Octagon. Quotes are short excerpts; the full conversation is in the episode.
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Dwarkesh Podcast, this episode and its artwork belong to Dwarkesh Patel. Octagon is not affiliated with the show; this page is an independent summary.
